Controller IP, System Power/Clock Management, Soft IP
Overview
The system control unit, is designed to provide a power and clock management functions for System-on-a-Chip (SoC) to handle operations of the chip that are the power enable sequence, boot-up sequence, operation frequency setting, and power-down sequence.
Technical Specifications
Related IPs
- I2C Controller IP – Master, Parameterized FIFO, APB Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
- I2C Controller IP – Master, Parameterized FIFO, AHB Bus
- I2C Controller IP – Master, Parameterized FIFO, AXI Bus