Configurable Watchdog Timer

Overview

The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technologies.

Key Features

  • AMBA APB3 bus
  • Configurable timeout interval
  • Standard and windowed mode
  • Register write protection
  • Stop in debug mode option
  • Fully synthesizable synchronous design with positive edge clocking
  • DFT ready

Benefits

  • Synthesizable RTL Verilog source code
  • Technology independent IP Core
  • Suitable for FPGA and ASIC
  • Silicon and FPGA proven
  • Easy SoC integration
  • Full implementation and maintenance support with individual approach
  • Flexible licensing scheme

Block Diagram

Configurable Watchdog Timer Block Diagram

Deliverables

  • Verilog RTL source code
  • Verification suite
  • Datasheet and integration guide
  • C-header file
  • Constraints
  • Technical support

Technical Specifications

Availability
Now
UMC
Silicon Proven: 130nm
×
Semiconductor IP