Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications

Overview

Key Features

• Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
• Full Transaction Layer, Data Link Layer and Physical Layer
• Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
• Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
• 125 MHz, 250 MHz, 500 MHz, 1GHz operation
• Supports PIPE PHY 8-, 16-, 32-, 64/80-bit interface including variable clock and variable data
• Application interfaces include the Synopsys native interface or the optional Arm AMBA 5 AXI, 4 AXI and 3 AXI application interface
• Optional embedded HyperDMA™ controller with up to 64 read and 64 write channels plus descriptor pre-fetch for high throughput with minimal SoC resource overhead
• Configurable and efficient retry buffer design for low latency and area
• Supports automatic lane reversal and polarity inversion
• Supports L1 sub-states and power gating for low-power consumption
• RAS data protection providing ECC and/or Parity protection for internal busses and memories
• Advanced debug capabilities for error injection and statistical monitoring
• Ultra-low transmit and receive latency and high accessible bandwidth
• Validated with Synopsys and third-party PHYs and verification IP
• Supports up to 8 virtual channels and up to 8 traffic classes
• Directly supports up to 32 physical functions and up to 256 virtual functions using SR-IOV and ARI – Optional extension up to 64K Virtual Functions

Benefits

• Designed to meet all required features of the PCI Express 6.0 (64 GT/s), 5.0 (32
• GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1
• (5 GT/s) and 1.1 (2.5 GT/s), and PIPE specifications
• Comprehensive suite of configurable controllers for Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode, and Multi-Port Switch applications
• Optimized for low power, small area and low latency
• PHYs include advanced built-in diagnostics, enabling at-speed production testing on low-cost digital tester
• Automotive Safety Integrity Level (ASIL) B Ready ISO 26262 certified controller and PHY IP
• Built-in applications in the verification IP accelerate testbench development
• Standards-compliant Synopsys Integrity and Data Encryption Security Modules protect data transfer and are pre-verified with Synopsys Controller IP for PCI Express for fast integration and low risk

Applications

• Enterprise computing, storage area networks, networking switches, and routers
• Wireless and mobile devices
• Industrial, automotive, and IoT
• Embedded systems and set-top boxes
• Graphics devices
• Desktops, laptops, workstations, and servers

Deliverables

• The coreConsultant utility to guide designers through the installation configuration, architectural exploration, verification, and implementation of the IP
• Verilog RTL code
• Example PHY interfaces
• ASIC and FPGA synthesis scripts
• Verification environment
• Synopsys Verification IP for the PCI Express
• Documentation: release notes, installation/integration guide, application notes, user manual

Technical Specifications