Compute Express Link (CXL) 2.0 Controller

Overview

Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic. There is also an CXL 2.0 Controller with AXI version for ASIC and FPGA implementations with support for the AMBA AXI protocol specification for CXL.io and either CPI or AXI for CXL.mem, and CPI for CXL.cache or the AMBA CXS-B protocol specification.

Key Features

CXL layer

Supports the CXL 2.0 specification
Implements the CXL.io, CXL.mem, and CXL.cache protocols
Supports all 3 defined CXL device types
Supports the PCI Express 5.0 base specification revision 1.0
Supports the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface width
Supports CXL device configurations
Supports operation at x16, x8, x4, x2, x1
Supports up to 64 Physical Functions (PF), 512 Virtual Functions (VF)
Supports PCI Express Advanced Error Reporting (AER)
Supports optional ECNs
Supports Port Bifurcation

User Interface layer

Native 256/512-bit transmit/receive low-latency interface for CXL.io traffic
Intel-defined CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic
User-selectable Transaction/Application Layer clock frequency (CXL.io)
Dedicated sideband interface for Reliability, Availability and Serviceability (RAS) features

Integrity and Data Encryption (IDE)

Implements the CXL 2.0 IDE specifications for CXL.cache/mem
Implements the PCI Express IDE ECN for CXL.io
Configurable IDE engine
Supports x1 to x16 lanes
Supports all device types
256-bit or 512-bit data bus for PCIe IDE
512-bit data bus for CXL.cache/mem IDE
Supports containment and skid modes
Supports early MAC termination
Supports multi-stream
Utilizes high-performance AES-GCM for encryption, decryption, authentication
PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
PCIe IDE automatic IDE prefix insertion and detection
PCIe IDE automatic IDE sync/fail message generation
PCRC calculation & validation
Efficient key control/refresh
Bypass mode

Benefits

Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
Ultra-low Transmit and Receive latency
Smart buffer management on receive side (Rx Stream) allows implementation of custom credit management schemes in the application logic
Merged Replay and Transmit buffer enables lower memory footprint
Optional Transaction Layer bypass allows for customer specific transaction layer and application layer
Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%

Block Diagram

Video

Demonstration of a CXL Interconnect on a FPGA-based design

In this video, we demonstrate the Rambus Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon processor as a host, connected to an FPGA board, instantiating Rambus' CXL Controller and CXL.mem test design.

Applications

HPC,
Cloud Computing,
AI,
Machine Learning,
Enterprise,
Networking,
Automotive,
AR/VR,
Test and Measurement

Deliverables

Verilog RTL,
Supporting Documentation

Technical Specifications

Foundry, Node

Any

Maturity

In production

Availability

Available

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