Combined Power-On-Reset and Low-voltage detector designed in Samsung Foundries 65nm LFR6LP
Bias current reference are provided by capacitor-less low quiescent LDO designed in the same process node (see qLR-Della-cl-ref-[1.8-5.5]-[0.9-1.4].02 )
Combined Power-On-Reset and Low-voltage detection in Samsung Foundries 65nm LFR6LP
Overview
Key Features
- Low-voltage monitoring solution for power-critical IoT applications
- The POR-LVD-[1.8-5.5]-[0.9-1.4].01 includes a Power-On-Reset used to monitor AVD and VDD supplies and to generate information to the SoC regarding the proper establishment of these AVD and VDD supplies.
- The detection threshold for VDD is fixed while the threshold for AVD monitoring is programmable. For a SoC in an ultra-low power mode, the circuits allowing a programmable threshold monitoring of AVD can be de-activated to reduce current consumption.
Technical Specifications
Foundry, Node
Samsung 65nm LP eFlash
Maturity
Pre-silicon
Samsung
Pre-Silicon:
65nm
LP
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