Vendor: Arm Ltd. Category: Network-On-Chip

Coherent Mesh Network

Scalable Mesh for Intelligent Connected Systems The Arm CoreLink CMN-700 Coherent Mesh Network is designed for intelligent connec…

Contact Provider Request Datasheet

Overview

Highly Scalable Mesh for Intelligent Connected Systems

The Arm CoreLink CMN-700 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications, including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Armv9 and Armv8-A processors, multichip configurations, and CXL attached devices. It can be customized across a wide range of performance points.

Key features

  • High-Performance, Scalable Coherent Mesh
    • The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.
  • Reduce SoC Integration Time
    • Socrates, a tool created by Arm, guides designers through the configuration and/or creating a viable interconnect fabric, reducing the time and complexity typically required for an implementing an interconnect mesh while simultaneously improving performance.
  • Maximize Compute Density
    • The CoreLink CMN-700 provides the highest performance coherent backplane for Armv9 systems from small, efficient access points to data center solutions maximizing compute density.
  • Coherent Multichip Links
    • CoreLink CMN-700’s CCIX/CXL Gateways extend the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, so system designers can attach more compute or acceleration with a shared virtual memory.
  • Support for Open Standards
    • The multichip links also support AMBA AXI5, ACE5-lite, CXS, and CCIX. CCIX is the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices.
  • Distributed System Cache
    • Keeping data on-chip greatly improves performance and efficiency. The integrated system cache is designed to decrease average CPU read latency and boost IO throughput workloads, such as networking and storage.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Arm CoreLink CMN-700
Vendor
Arm Ltd.
Type
Silicon IP

Provider

Arm Ltd.
HQ: Great Britain
Arm technology is defining the future of computing. Our energy-efficient processor designs and software platforms have enabled advanced computing in more than 240 billion chips and our technologies securely power products from the sensor to the smartphone and the supercomputer. Together with 1,000+ technology partners, we are enabling artificial intelligence to work everywhere, and in cybersecurity, we are delivering the foundation for trust in the digital world – from chip to cloud. The future is being built on Arm.
Contact Arm Ltd.

Learn more about Network-On-Chip IP core

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures

Ensuring Network-on-Chip (NoC) security is crucial to design trustworthy NoC-based System-on-Chip (SoC) architectures. While there are various threats that exploit on-chip communication vulnerabilities, eavesdropping attacks via malicious nodes are among the most common and stealthy. Although encryption can secure packets for confidentiality, it may introduce unacceptable overhead for resource-constrained SoCs.

Why verification matters in network-on-chip (NoC) design

In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Accelerating RISC-V development with network-on-chip IP

In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.

Network-on-chip (NoC) interconnect topologies explained

Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.

Frequently asked questions about NoC IP cores

What is Coherent Mesh Network?

Coherent Mesh Network is a Network-On-Chip IP core from Arm Ltd. listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP