Coherent Mesh Network

Overview

Highly Scalable Mesh for Intelligent Connected Systems

The Arm CoreLink CMN-700 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications, including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Armv9 and Armv8-A processors, multichip configurations, and CXL attached devices. It can be customized across a wide range of performance points.

Key Features

  • High-Performance, Scalable Coherent Mesh
    • The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.
  • Reduce SoC Integration Time
    • Socrates, a tool created by Arm, guides designers through the configuration and/or creating a viable interconnect fabric, reducing the time and complexity typically required for an implementing an interconnect mesh while simultaneously improving performance.
  • Maximize Compute Density
    • The CoreLink CMN-700 provides the highest performance coherent backplane for Armv9 systems from small, efficient access points to data center solutions maximizing compute density.
  • Coherent Multichip Links
    • CoreLink CMN-700’s CCIX/CXL Gateways extend the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, so system designers can attach more compute or acceleration with a shared virtual memory.
  • Support for Open Standards
    • The multichip links also support AMBA AXI5, ACE5-lite, CXS, and CCIX. CCIX is the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices.
  • Distributed System Cache
    • Keeping data on-chip greatly improves performance and efficiency. The integrated system cache is designed to decrease average CPU read latency and boost IO throughput workloads, such as networking and storage.

Technical Specifications

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Semiconductor IP