The Spectrum sensing core blindly detects occupied sub-carriers within a wide-band spectrum. The algorithm implemented in this core uses a patented algorithm (US 8,630,377 B2). The efficient real time implementation makes this core an ideal candidate to be used in cognitive radios. Spectrum sensing core is a fully parallel implementation which gives real time spectrum sensing capabilities allowing little to no interference to the incumbent. This spectrum sensing core is targeted to be used in radios developed based on IEEE802.22 standard.
This module is written in VHDL, capable of being used on any FPGA/ASIC architecture.
Cognitive Radio IP Core
Overview
Key Features
- Parameterisable Input bit width
- Parameterisable FFT size
- Parameterisable HMM window length
- Parameterisable PS bit width
- Detects multiple interferers
- Fully synchronous design using only one clock
- Automatic internal rescaling
- Low latency
- Optimized design allowing high-speed operation
- User friendly control interface
- Silicon verified in multiple devices
- Can be tailored to customer needs
- Area/Power efficient architecture
Block Diagram
Deliverables
- Netlist or synthesizable RTL source code in VHDL
- Comprehensive verification test bench and vectors in VHDL
- Integration documentation and user guide
Technical Specifications
Availability
Now
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