Clock Verification IP (VIP)

Overview

Clock Verification IP can be used to generate clock signals in testbench.

There is no license required to use Clock VIP.

Key Features

  • SystemVerilog interface based
  • Supports master mode and pass-through mode both
  • Example design delivered in IP integrator

Technical Specifications

Short description
Clock Verification IP (VIP)
Vendor
Vendor Name
×
Semiconductor IP