CLICK - The universal solution of power gating for the whole SoC

Overview

TSMC 180 eLL, CLICK, power gating cells to create a ring of switches in order to ease the integration of hard macro and provide automatic control of in-rush current during wake-up.

Key Features

  • Flexibility of in-rush current and wake-up time management
  • Allows a smart control of the trade-off between wake-up time and in-rush current
  • Automated wake-up sequence including isolation and retention signal management
  • Programmable limitation of in-rush current controlled by Transition Ramp Controller (TRC) enables a ? correct-by-construction ? implementation
  • The flexibility to easily adjust in-rush current and/or minimize wake up time before and after fabrication (no need for iterative and complex simulation)
  • Ease of integration thanks to a universal solution
  • One power gating solution at SoC level
  • Enables easy integration of hard macros and the implementation of power gating on blocks designed with any library from any provider (e.g. 12T free library)
  • Methodology for an automatic computation of the ring with optimal number and size of power switches
  • Script for automatic and optimized power ring insertion for polygonal islands
  • Anticipate IR-Drop, load current and in-rush budgets at early stage thanks to Abacus
  • Simplify your design thanks to ring style implementation
  • Allows power gating without aggravating an already congested design
  • Ring style is more flexible to deal with global IR-Drop optimization over the design implementation even though Grid style is more flexible than Ring style for local IR-Drop optimization
  • Allows to modify/optimize the ring to reach a better IR-Drop or a lower leakage without re-routing the block
  • Specific power switches for ring implementation with built-in command signals and power supply routing
  • Power leakage optimized
  • Up to 99.9% power leakage savings at SoC level (only switch leakage)
  • Optimized management of the IR-Drop vs. leakage trade-off thanks to the abacus
  • Dedicated documentation
  • Dedicated Application Notes to complete the standard LP flow

Technical Specifications

Maturity
Pre-silicon
TSMC
Pre-Silicon: 180nm ELL
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Semiconductor IP