ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP
Overview
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-5 GTP is a customizable core that can be used to evaluate and monitor the health of Virtex-5 GTP Transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the MGTs. Communication logic is also included, to allow the design to be runtime accessible through JTAG. The IBERT core is a self-contained design, and when it is generated, will run through the entire implementation flow, including bitstream generation.
Key Features
- Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core.
- Has user-selectable number of Virtex-5 GTP Transceivers.
- Each transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and datapath width.
- Requires a system clock that can be sourced from a pin or one of the enabled MGTs.