CCSDS turbo encoder with sync marker, pseudo randomiser and input memory

Overview

Key Features

• 16 state CCSDS compatible turbo encoder
• Rate 1/2, 1/3, 1/4 and 1/6
• Interleaver sizes from 1784 to 16056 bits in multiples of 1784
• Includes sync marker, optional pseudo-randomiser and ping-pong input memory
• Up to 706 MHz internal clock
• Up to 346 Mbit/s encoding speed
• Serial continuous encoded data out
• 254 or 216 6-input LUTs with 1 or 2 18 kB RAMB18s
• Asynchronous logic free design
• Available as EDIF and VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.

Block Diagram

Deliverables

• All Licenses
• EDIF Virtex-II, Spartan-3, Virtex-4 Core
• VHDL Virtex-5, Spartan-6, Virtex-6, 7-Series, UltraScale, UltraScale+ Core
• Test vector generator
• ASIC License
• VHDL ASIC Core

Technical Specifications