The LCD01C is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control decoder. A regular quasic–cyclic LDPC code with 511x511 square circulants with weight 2 in the parity check matrix is used. There are 2x16 circulants, resulting in a check node degree of 32 and a variable node degree of 4.
In each clock cycle, 12 check nodes (12x32 = 384 messages) or 96 variable nodes (96x4 = 384 messages) are fully decoded. Each iteration requires 86 clock cycles to calculate the check or variable messages plus a 7 clock cycle pipeline delay. The scaled min–sum iterative decoding algorithm is used.
Optional early stopping allows the decoder to reduce power consumption with little degradation in performance. The decoder contains two sets of message memories so that check and variable calculations can be performed in parallel. Two input memories are used to buffer the input data.
CCSDS (8160,7136) LDPC Decoder
Overview
Key Features
- CCSDS compatible
- Rate 223/255 (8160,7136)
- Includes ping-pong input and output memories
- Up to 488 MHz internal clock
- Up to 3.5 Gbit/s with 10 decoder iterations
- 6-bit sign-magnitude input data
- Up to 64 iterations
- Scaled min-sum decoding algorithm
- Optional power efficient early stopping
- Parity check output
- 23,453 6-input LUTs, 166 18KB BlockRAMs. 26,800 Altera ALUTs, 166 M9Ks.
- Asynchronous logic free design
- Available as EDIF and VHDL core for Xilinx FPGAs under SignOnce IP License. ASIC, Intel/Altera, Lattice and Microsemi/Actel cores available on request.
Block Diagram
Deliverables
- All licenses
- EDIF Virtex-II, Spartan-3, Virtex-4 Core
- VHDL Virtex-5, Spartan-6, Virtex-6, 7-Series, UltraScale, UltraScale+ Core
- Test vector generation software
- Channel simulation software
- VHDL ASIC License
- VHDL ASIC core
Technical Specifications
Availability
Now