The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 512 are specially designed for telecommand applications, but the excellent error correction performance makes it an ideal fit for further applications with highest demands on forward error correction.
CCSDS 231.0 LDPC Encoder and Decoder
Overview
Key Features
- Support for code rate 1/2
- Uncoded block sizes of 64 and 256 bits
- Compliant with “TC synchronization and channel coding, Recommended Standard, CCSDS 231.0-B-3, Blue Book, September 2017”.
Benefits
- Gains of up to 3 dB compared to Viterbi decoders
- Low-power and low-complexity design
- Layered LDPC decoder architecture, for convergence behavior that is twice as fast as non-layered LDPC decoders
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
- Optional fixed number of iterations for fixed latency of blocks with the same code rate and block length
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
- Collection of statistic information (number of iterations, decoding success, number of modified bits)
- Available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip).
Applications
- Telecommand communication
- Free space optical (FSO) communication
- Further applications with the highest demands on forward error correction
Deliverables
- VHDL source code or synthesized netlist
- HDL simulation models e.g. for Aldec’s Riviera-PRO
- VHDL testbench
- bit-accurate Matlab, C or C++ simulation model
- comprehensive documentation