CCSDS 131.2 SCCC Turbo Encoder and 64-APSK Modulator
Overview
The IPrium-CCSDS-SCCC-Modulator-Encoder IP Core implements the CCSDS modulation standard 131.2-B. The IP Core is a complete digital QPSK, 8-PSK, 16-APSK, 32-APSK and 64-APSK modulator with an integrated Serially Concatenated Convolutional turbo encoder (Turbo SCCC), optimized for high-capacity satellite systems.
Key Features
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
- Fully verified and real-time tested on a FPGA based development platform
- Considerations for easy ASIC integration
- Validated on IPrium Evaluation Boards
Deliverables
- VQM/NGC/EDIF netlists for Intel (Altera) Quartus Prime, Xilinx Vivado/ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
- IP Core testbench scripts
- Design examples for Intel (Altera), Xilinx, Lattice, and Microsemi (Actel) evaluation boards
- Free 1 year warranty and support period
Technical Specifications
Maturity
Silicon proven
Availability
Now