CAN Bus Controller with Message Filter (Mailbox concept)

Overview

CANmodule-III is a full functional CAN controller module that supports the concept of mailboxes. It is compliant to the international CAN standard defined in ISO 11898-1.

It contains 16 receive buffers, each one with its own message filter, and 8 transmit buffers with prioritized arbitration scheme. For optimal support of Higher Level Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes as well.

The design is written in technology independent HDL and can be mapped to ASIC and FPGA architectures and makes use of on-chip SRAM structures. An AMBA Advanced Peripheral Bus (APB) interface enables smooth integration into ARM based SOC’s. This full synchronous bus interface can easily be connect to other system buses.

Key Features

  • Standard Compliant
    • Full CAN 2.0B compliant
    • Conforms to ISO 11898-1
    • Maximum baudrate of 1 Mbps with 8 MHz system clock
  • Receive Path
    • 16 receive buffers
    • Each buffer has its own message filter
    • Message filter covers: ID, IDE, RTR, Data byte 1 and Data byte 2
    • Message buffers can be linked together to build a bigger message array
    • Automatic remote transmission request (RTR) response handler
  • Transmit Path
    • 8 Tx message holding registers with programmable priority arbitration
    • Message abort command
  • System Bus Interface
    • AMBA 2.0 Advanced Peripheral Bus Interface
    • Full synchronous zero wait-states interface
    • 8, 16, or 32-bit wide data path
    • Status and configuration interface
  • Programmable Interrupt Controller
    • Local interrupt controller covering message and CAN error sources
  • Test and Debugging Support
    • Listen only mode
  • SRAM Based Message Buffers
    • Optimized for low gate-count implementation
    • Single port, synchronous memory based
    • 100% Synchronous Design

Block Diagram

CAN Bus Controller with Message Filter (Mailbox concept) Block Diagram

Deliverables

  • VHDL or Verilog RTL Source Code
  • Verification Suite
    • Functional Testbench including CANbus tranceiver model and additional CAN nodes
  • Synthesys Script
  • Data Sheet
  • User Guide
  • Hotline Support by means of phone, fax and e-mail

Technical Specifications

Foundry, Node
Technology independent
Maturity
Silicon proven in ASIC and FPGA Technologies
Availability
now
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Semiconductor IP