Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane

Overview

Key Features

• SLVS-EC ver.2.0 / MIPI D-PHY v2-1 compliant
• Supporting for four kind Differential Input Signals
• 1) SLVS-EC (Maximum 5.0Gbps)
• 2) MIPI D-PHY (Maximum 4.5Gbps)
• Xtal Input Clock Frequency Selectable 24MHz / 48MHz / 72MHz
• Maximum Input Clock Frequency ~2.25GHz (D-PHY mode)
• Power Supply : Vcc=1.8V (IO and Analog) Vdd=0.9 V (Inside Core)
• Maximum Lane Number : 4-Lane
• 10-bit/Lane Parallel Outputs (SLVS-EC)
• 8-bit/Lane Parallel Outputs (MIPI D-PHY)
• Including Power Down Mode
• Including "Hi-Z" Detect Circuit for SLVS-EC
• TSMC 28nm HPC+ Process
• Poly Direction: South-North
• Various process porting support available ( Please contact us. )
• Supporting Link-layer: CD12822IP soft macro

Benefits

• This IP is supported almost CMOS Image Sensor. Thus if when the customer want to use customer's LSI other system set, the customer don't need to change IP, because this IP can change Interface type to same PAD for changing mode pin.
• The system customer can select from many CMOS image sensor for using out IP.
• We are updating CMOS Image Sensor's modelnumber of verify operation for getting information from customer and ourself at all time.
• If the customer need combo Link-layer, we can provide them and can support system.
• We are provided CIS and TX Verilog Model. Thus the customer can confirm function by verilog simulation status.

Applications

• Camera Application
• Security Camera
• Mobile-Phone Camera
• DSC(Digital Still Camera)
• Medical Camera
• SLR
• 3D Camera
• Camcorder
• ISP(Image Signal Processer)

Deliverables

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Combo Link Layer IP(CD12822IP) and FPGA Board(Option)

Technical Specifications