Vendor: Minerva Technology Category: Video Processing

H.264 (AVC) CABAC Decoder IP Core

CABAC Decoder IP Core performs stream decoding that was derived by context-adaptive binary arithmetic coding algorithms.

Contact Provider Request Datasheet

Overview

CABAC Decoder IP Core performs stream decoding that was derived by context-adaptive binary arithmetic coding algorithms. The IP Core is designed to accelerate the decoding of compressed video AVC (H.264) format.

CABAC Decoder IP Core performs streams decoding that were derived by algorithms CABAC (Context-Adaptive Binary Arithmetic Coding). IP Core is designed for hardware acceleration of entropy arithmetic decoding of AVC (H.264) streams.

Key features

  • Fully complies with ISO / IEC 14496-10 / ITU-T H.264
  • Profile: Main
  • High performance. Bit rates — up to 40 Mbit/s at a clock frequency of 200 MHz
  • Hardware initialization and binarization contexts
  • Compact core size. Can be used for FPGA low-price range.

What’s Included?

The IP Core is available as either a netlist or in source code, and includes everything necessary for a successful implementation of the customer's project.

The netlist includes:

  • Synthesized netlist for the specified FPGA device.
  • Testbench and bit-accurate model.
  • Place-and-route script.
  • Simulation script.
  • Documentation, including detailed specifications and instructions for project integration.

Specifications

Identity

Part Number
H.264 (AVC) CABAC Decoder IP Core
Vendor
Minerva Technology
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Minerva Technology
HQ: Russia
Minerva LLC is a start-up company that develops hardware and software for real time data processing. Company is focusing on the effective algorithm of digital signal processing and video data compression development and realization.
Contact Minerva Technology

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is H.264 (AVC) CABAC Decoder IP Core?

H.264 (AVC) CABAC Decoder IP Core is a Video Processing IP core from Minerva Technology listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP