H.264(AVC) CABAC Decoder IP Core

Overview

Key Features

• Fully complies with ISO / IEC 14496-10/ITU-T H.264;
• Profile: Main;
• High performance. Bit rates - up to 50 Mbit/s at a clock frequency of 180 MHz;
• Hardware initialization and binarization contexts;
• Compact core size. Can be used for FPGA low price range.

Deliverables

• The IP Core is available either netlist (netlist) or in source code, and includes everything necessary for a successful implementation of the project customer.
• The netlist includes:
  • Synthesized netlist for the specified device FPGA;
  • Testbench and bit accurate model;
  • Place @ Rout script;
  • The script for the simulation;
  • Documentation, including detailed specifications and instructions for the integration of the project member.

Technical Specifications