Bandgap Voltage Reference - Low Integrated Noise (57.2µVrms) TSMC 40nm

Overview

This macro-cell is a low power voltage reference generator core designed for TSMC 40nm CRN40LP CMOS technology. The core is ideal as a general purpose reference voltage in applications where low output noise and wide PSRR band are critical. The circuit generates an unbuffered 570mV, temperature compensated bandgap voltage reference (57ppm/ C). Internal start-up circuit allows the reference is available as soon as the power supply ramps up, so none enable/disable function is necessary to start it up. It has three trimming bits for the coeficient temperature. It has a general purpose 3.2µA PTAT output current. The core is easily re-targeted to any other CMOS technology.

Key Features

  • Vref=0.57V ±3.8% (without trimming)
  • 17.2uA current consumption in active mode
  • Supply voltage: 1.0–1.32V
  • Output noise: 57.2uVrms (integrated up to 20MHz)
  • PSRR 50dB @ 20MHz
  • Automatic start-up as soon as power supply starts
  • Indicative area: 0.047mm2

Block Diagram

Bandgap Voltage Reference - Low Integrated Noise (57.2µVrms) TSMC 40nm Block Diagram

Applications

  • Voltage Reference for ADCs

Deliverables

  • Datasheet/Integration Guide
  • HDL Model
  • Flat GDSII database/LVS netlist
  • Customer Support

Technical Specifications

Foundry, Node
TSMC 40nm
Maturity
Silicon Available
Silterra
Pre-Silicon: 180nm
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Semiconductor IP