The AMBA-AXI VIP provides a complete solution for verification of AMBA-AXI protocol version 2.0. The AXI verification IP is fully compatible with standard AXI 3 protocol. This VIP is supported natively in System Verilog UVM.
AXI Verification IP
Overview
Key Features
- Separate address/control and data phases
- Support for unaligned data transfers using byte strobes
- Burst-based transactions with only start address issued
- separate read and write data channels to enable low-cost Direct Memory Access (DMA)
- Ability to issue multiple outstanding addresses
- Out-of-order transaction completion
- Easy addition of register stages to provide timing closure
Benefits
- Availability in pure System Verilog and UVM
- Unique development to ensure highest level of quality
- Availability of Compliance & Regression test suites
- Unique and customizable licensing models
- Supports directed random and fully random tests
- Supports environment configuration of VIP based on DUT
- Monitors and Checkers for protocol violation
- Coverage model for functional coverage
Block Diagram
Deliverables
- VIPuser guide
- AXI VIP encrypted source code
- Sample Testbench top
- Sample scoreboard
- Assertions and coverage model
Technical Specifications
Related IPs
- I2C Controller IP – Master, Parameterized FIFO, AXI Bus
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
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