AXI SRAM Bridge

Overview

AXI4 to memory bridge with SECDEC and exclusive access support

axi2mem bridge should be used to connect standard RAM or ROM blocks with plain CE-WE input control interface to AXI4 bus. It supports exclusive accesses (AXI4 transactions with AxLOCK=0b1 according to AXI4 specification).

Key Features

supports all types and sizes of AXI4 read bursts
supports all types and sizes of AXI4 write bursts
supports AXI4 exclusive accesses
configurable address and data widths
configurable AXI4 ID width
configurable size of connected ROM/RAM block (based on address width)
check ROM/RAM address validity option
SECDED option with interrupts generation and failed address storage (controlled/accessed via APB interface)
Read-Modify-Write option to support non-byte-enable memory (this option is always enabled together with SECDED option)

Block Diagram

Applications

Deliverables

RTL code
Verification suite

Technical Specifications

Maturity

FPGA proven

Availability

Available

Request Info

Related IPs

RapidIO to AXI Bridge (RAB)
AXI to AHB Lite Bus Bridge
AXI to APB Bus Bridge
SPI to AXI Bridge
AXI to APB Bus Bridge
PCI Express to AMBA 4 AXI/3 AXI Bridge