The ability to purchase AXI BFM has been discontinued as of December 1, 2016. The existing AXI-BFM licenses will work perpetually in releases through 2016.4, but will not be supported after the Vivado 2016.4 release.
AXI BFM will be replaced by Xilinx AXI Verification IP in CY2017. For more information please contact your Local Xilinx Sales Contact.
AXI Bus Functional Model (BFM)
Overview
Key Features
- Supports all protocol data widths and address widths, transfer types and responses
- Transaction level protocol checking (burst type, length, size, lock type, cache type)
- Behavioral Verilog Syntax
- Verilog Task-based API
- Delivered in ISE, enabled by a Xilinx-generated license
- Verilog and VHDL example designs and test benches delivered standalone or through CORE Generator for RTL design
- Integrated with XPS as a pcore or as an option with CIP wizard
- Supported Simulators: Aldec Riviera-PRO, Cadence Incisive Enterprise Simulator, ISE Simulator, Mentor Graphics ModelSim and Synopsys VCS