AXI 2.0 USB Device IP

Overview

USB is a generic interface in the modern days to connect to various high speed data peripherals. Many USB device/client controllers are introduced in the embedded systems market, which enables interfacing a host microcontroller to quickly and easily connect to a USB host such as a PC or industrial PC. One of the major limitations on these controllers is the bottle neck on data rate imposed by the interface between the host microcontroller and the USB device controller which more often is a serial UART interface, SPI interface, JTAG interface, or FIFO interface. In FPGA based embedded systems with reconfiguration capability, it is desirable to implement this USB controller on-chip and thus implement an SoC.

Key Features

AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
USB serial interface engine implemented to support USB2.0 full speed and high speed interface
Supports ULPI interface to external PHY chip
Supports control, bulk, interrupt and isochronous transfers on USB interface
8 endpoints instantiated with endpoint 0 as the control endpoint
Handles USB enumeration process

Benefits

With an addition of a low cost external USB PHY chip, a USB device can be realized using this IP in no time. The user interface to the host microcontroller instantiated on the FPGA is provided in an AXI interface format and thus, the USB controller is made as a memory mapped device accessible from the industry standard AXI bus from the host microcontroller.

Applications

We present a USB device controller IP to implement on an FPGA in an embedded system. It carries out all tasks like USB device enumeration, endpoint instantiations, etc. and enables bulk, isochronous, interrupt and control packet transfers over USB.

Technical Specifications

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