AVSBus Synthesizable Transactor provides a smart way to verify the AVSBus component of a SOC or a ASIC in Emulator or FPGA platform.The SmartDV's AVSBus (Adaptive Voltage Scaling) Synthesizable Transactor is fully compliant with standard AVSBus Specification and provides the following features.
AVSBus Synthesizable Transactor
Overview
Key Features
- Follows AVSBus basic specification as defined in PMBus 1.3.1 Part III Specification
- Supports data width upto 64 bits
- Support AVSBus Master and Slave functionality
- Supports 3-wire ,2-wire AVSBus interface
- Supports all AVSBus Commands as per specs
- Supports clock Resynchronization
- Supports timeout detection and generation
- Supports following AVSBus topologies
- Single Master and Single Slave
- Multiple links
- Supports insertion of various errors
- NACK insertion by Slave
- CRC Error
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Complete regression suite containing all the LVDS testcases
- Synthesizable transactors
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
Technical Specifications
Short description
AVSBus Synthesizable Transactor
Vendor
Vendor Name