Auxiliary ADC - 12-bit Successive Approximation Register (SAR) ADC

Overview

This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.

This ADC has dual input modes, i.e. single-ended and differential-ended. Differential-ended mode is used in noisy environment; whereas single-ended mode is used in clean environment. In single-ended input mode, 12 channels’ input signals can be selected. In differential-ended input mode, 6 pairs’ differential input signals can be selected.

The ADC has dual speed modes – 1Msps or 200Ksps, working in 200K mode could save some power.
 

It is suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.

Key Features

  • Silicon proven in 22, 28, 40, 55, 65, 110, 130, 180nm from SMIC, HHgrace, Global Foundries and Samsung
  • Resolution: 12-bit
  • Data Rate: 1Msps/200Ksps
  • DNL: ±1.5 LSB, INL: ±3 LSB
  • 62dB SNR @FIN=20KHz 1Msps
  • Single-ended or Differential-ended Modes
  • Analog Input Range
    •   VREFH to VREFL, could be rail-to-rail
  • Low Power Consumption
    •   500uA@1MSPS
    •   200uA@200KSPS
  • Flexible Control Logic

Block Diagram

Auxiliary ADC - 12-bit Successive Approximation Register (SAR) ADC Block Diagram

Technical Specifications

Foundry, Node
GLOBALFOUNDRIES 28nm SLP
Maturity
Available on request
GLOBALFOUNDRIES
Pre-Silicon: 28nm SLP
SMIC
Pre-Silicon: 28nm , 40nm LL , 55nm G , 65nm LL , 110nm G , 180nm G
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Semiconductor IP