Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using very high speed transceivers.
The ALSE Aurora 64B/66B IP core is a very compact and optimized implementation of this protocol, also developed and verified to ensure full compatibility with the Xilinx core (interoperability has been tested and demonstrated).
This IP targets mainly Intel FPGAs but is available for other vendors, and potentially for ASIC projects.
Compared to the 8B/10B version of the Aurora protocol, the 64B/66B flavor addresses the highest lanes speeds (when 8B/10B typically stops around 6 GBs per lane).
It also offers an effective bandwidth of up to 97%, instead of 80% for 8B/10B.
Our IP therefore provides an efficient way to interconnect Intel and Xilinx FPGAs, or any other chip(ASIC, ASSP, etc …) using the Aurora 64B/66B protocol.
Aurora 64B/66B IP Core
Overview
Key Features
- Full implementation of Aurora protocol
- Full-Duplex and Simplex Tx operation.
- 64-bits user datapath
- Framing and Streaming interface
- Up to 16 transceiver lanes per Aurora instance
- User K-block interface
- Native Flow Control
- User Flow Control
- Additional CRC for PDU frames
- Clock compensation
- Complete Interoperability with Xilinx Aurora 64 core
- Per lane polarity inversion and skew compensation.
- AXI and Avalon-ST Streaming compatible.
Block Diagram
Technical Specifications
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