Low Power Audio CODEC/ADC/DAC

Overview

The Audio CODEC IP is a low power, high resolution, stereo audio solution which leverages Sigma-Delta noise-shaping technology. The ADC, DAC, PGA, and power amplifier are integrated to provide a complete solution. Innosilicon Audio CODEC IP offers reliable solutions for audio signal conversion in high end consumer, automotive, multimedia, and other digital audio systems.

The Audio CODEC IP consists of ADC channels, DAC channels, and bias circuit. The ADC channel is used to convert analog audio signals to digital signals. Each ADC channel contains input PGA, ALC, Sigma-Delta modulator, and digital filter. The DAC channel is used to convert digital audio signals to analog signals. Each DAC channel contains Sigma-Delta modulator, DCT, and power amplifier. The bias circuit generates voltage and current reference.

Key Features

  • 24 bits DAC with 93dB SNR
  • Supports 1~8 DAC channels
  • Supports 16Ω to 32Ω headphone output or line output
  • Low power: 5mA for stereo playback
  • 24 bits ADC with 92dB SNR
  • Supports 1~8 ADC channels
  • Supports differential and single-ended microphone or line input
  • Low power: 5mA for stereo recording
  • Supports sampling rate of 8kHz/12kHz/16kHz/24kHz/32kHz/44.1kHz/48kHz/96kHz
  • Supports Automatic Level Control (ALC) for smooth audio recording
  • Supports Mono, Stereo, 5.1 and 7.1 HiFi channel performance
  • Supports programmable input and output analog gains
  • Built-in digital interpolation and decimation filter
  • The area correlates strongly with process node and channel count. please refer to the detailed datasheet

Benefits

  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include:
    • Test chips and test boards
    • FPGA integration support
    • Chip level integration

Block Diagram

Low Power Audio CODEC/ADC/DAC Block Diagram

Deliverables

  • Databook and detailed physical implementation guides
  • Complete set of timing models
  • Library Exchange Format (LEF)
  • Encrypted Verilog Models
  • Layout vs. Schematic (LVS) report
  • GDSII database for foundry merge

Technical Specifications

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Semiconductor IP