A ATA-7 compliant host controller core to interface to ATA devices like hard-disks, CD and DVD drives. This core is targeted for SOC implementations in ASIC and FPGA.
ATA-7 (UDMA 133) Host controller
Overview
Key Features
- PIO modes 0-4
- Multi-word DMA modes 0-2
- Ultra DMA modes 0-6
- Programmable timings for PIO and DMA modes
- Support for Ultra DMA pause and termination
- Standard slave Wishbone interface to microprocessor/microcontroller
- Interrupt generator for IRQ driven software driver implementation
- Transparent (pass through) access from processor interface to device task registers
- DMA engine and master Wishbone interface for data transfer
- Small register FIFOs for transmit and receive data
- 66MHz clock for UDMA133 (mode 6) operation
Benefits
- Flexible
- Compact
- Cost-effective
- Many Shipping Products
Block Diagram
Deliverables
- Verilog Source Code
- Test Bench
- Sample Syntheis scripts
- Dcumentation
- Refernce Resign
Technical Specifications
Foundry, Node
any
Maturity
production
Availability
Now