ARM HSSTP PHY with Link Layer

Overview

Key Features

• Standards Compliance
• ARM HS-STP v6.0
• ARM Coresight DDI 0314H
• Xilinx Aurora 8b/10b v2.2
• IEEE 1149.1
• High-Speed Data Transfer
• Up-to 6.25/12.5Gbps per lane
• Up-to 8 lanes, for a combined total of 50Gbps
• Low Power
• Automatic shut-off when not enabled ensures minimum power consumption
• Simple configuration interface
• Small register configuration space
• Simple interface, can be easily connected to an standard APB bus, or similar
• Minimal setup, with automatic start-up when reset is de-asserted
• On-Chip IO ring compatibility
• Designed as an IO-ring component
• Small footprint
• Wire-Bond and Flip-Chip compatible
• Clocking
• Flexible clocking options, including internal and external, direct or crystal-based
• Optional Features
• JTAG Interface
• Embedded TAP controller
• Extensive Test and Debug Features
• Scan
• DC JTAG
• Serial Debug Access

Benefits

• Fully integrated/ hardened drop-in solution along with Link Layer
• Small foot print
• Low power
• Comprehensive features

Block Diagram

Applications

• The VG3ST6 can be paired with an HS-STP compatible receiver system to create a flexible debugging platform customizable for nearly every silicon bring-up strategy. The figure shows a typical example of application.

Deliverables

• PHY
• Abstract LEF
• Behavioral Model Verilog
• Timing Model .lib
• High-speed IO Model hSpice
• LVS Netlist cdl
• Physical database GDSII
• Documentation pdf
• LINK Layer ( Aurora )
• RTL Verilog
• Synthesis/ Timing SDC
• Documentation PDF
• Test Bench Verilog

Technical Specifications