Arm Cortex-R5
Overview
The Arm Cortex-R5 processor forms a simple migration path from the Cortex-R4 processor, and onwards to the higher performance Cortex-R8 and Cortex-R52 processors. The Cortex-R5 processor builds on the feature set of the Cortex-R4 with enhanced error management, extended functional safety, and SoC integration features, for use in deeply embedded real-time and safety-critical systems.
Key Features
- Higher system performance and Advanced system level integration features - Dual-core configurations which enable twice the performance with Accelerator Coherency Port (ACP) and Micro Snoop Control Unit (micro SCU) maintaining data cache coherency with DMA I/O for both cores.
- Improved reliability and safety features - Low-Latency Peripheral Port (LLPP), enhanced Memory Protection Unit (MPU) and enhanced ECC support.
- Lock-step configurations - Second core provides redundancy for safety critical applications.
- Extended functional safety support - Safety Documentation simplifies the certification effort for standards such as ISO26262 and IEC 61508, and enables higher levels of certifications.
Benefits
- Improves reliability and high error resistance safety features for safety critical applications including bus Error Checking and Correction (ECC).
- Ability to detect both systematic and random faults in the core.
- Support for dual-core lock-step and split-lock configurations and advanced system level features to achieve twice the performance.
- Simplified certification effort with the optional Safety Documentation Package for standards such as ISO 26262 and IEC 61508, and enable higher levels of certification to be obtained.
Block Diagram
Applications
- Automotive
- Industrial
- Mass storage