ARINC 825 Verification IP

Overview

ARINC 825 Verification IP implements the digital transmision system have been specified for inter-unit and inter-systems communications on board transport aircraft. ARINC 825 Verification IP provides an smart way to verify the ARINC 825 standard data transmission and control interfaces between transmitter and receiver.The SmartDV's ARINC 825 Verification IP is fully compliant with ARINC specification 825 - 2 and provides the following features.

ARINC 825 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

ARINC 825 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports ARINC specification 825 - 2.
Supports one of the following data rates
- 83.33 Kbit/s
- 125 Kbit/s
- 250 Kbit/s
- 500 Kbit/s
- 1 Mbit/s
The model has a rich set of configuration parameters to control ARINC 825 functionality.
Supports one-to-many communication and also peer-to-peer communication.
Supports all the four frame types.
- Data frames
- Remote frames
- Error frames
- Overload frames
Remote frame support.
- Automatic transmission after reception of remote transmission request (RTR).
- Automatic receive after transmission of an RTR.
Supports all the five types of error insertion and detection.
- Bit errors
- Stuff errors
- CRC errors
- Format errors
- Acknowledgement errors
Supports all the node service interface as per ARINC 825 -2 specification.
- Node service concept[NSC]
- Node identification service[IDS]
- Node synchronization service[NSS]
- Data upload service[DUS]
- Data download service[DDS]
- Bit control service[BCS]
- Non-volatile storage service[NVS]
- Node-ID setting service[NIS]
- Service control service[SCS]
Tracks TEC/REC error counter and fault states.
Support Broadcast and acknowledgement by all nodes.
Supports Bit by bit Arbitrations.
Glitch insertion and detection
Re-transmission of corrupted messages.
Status counters for various events on bus.
Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Supports constraints Randomization.
Callbacks in transmitter,receiver and monitor for various events.
Built in functional coverage analysis.

Benefits

Faster testbench development and more complete verification of ARINC 825 designs.
Easy to use command interface simplifies testbench control and configuration of Transmitter,Receiver and Monitor
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the ARINC 825 testcases.
Examples showing how to connect various components, and usage of Transmitter,Receiver and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info