Great River's ARINC 818 IP Core provides an easy way to implement ARINC 818–compliant interfaces in Xilinx and Altera PLDs. The core can achieve ARINC 818 interfaces up to 4.25 Gbps. The core can be used for transmit-only, receive-only, or transmit-and-receive applications.
The core has many flexible compile-time settings, allowing for various link speeds, line segmentations, and line-synchronization methods. It can be configured for various resolutions and pixel packing methods. Ancillary data can use default values set at compile time, or data can be updated in real time via register interface.
ARINC 818 Transceiver
Overview
Key Features
- Available for most Xilinx and Altera FPGAs with Gigabit transceivers
- Supports all ARINC 818 Link speeds up to 8.5 Gbps
- Simple pixel bus interface
- Compile time configurable for ADVB video format (resolution, pixel type, etc.)
- Supports transmit only, receive only, or full transceiver instantiation
- Configurable for various line segmentations
- Supports line synchronous transmission
- Built-in pixel packing/unpacking
- Link status & detection outputs (CRC_error, SOF/EOF_det, etc.)
- Tx Object 0 Ancillary data real-time update
- Tx Object 0 default values compile-time settable
- Complete Object 0 Ancillary data recovery on Rx
- Airborne Certification package available
Block Diagram
Deliverables
- VHDL and Encripted VHDL files
- Instantiation templates
- VHDL test bench
- UCF file templates
- Coregen output files
- User’s Guide
- Optional Aerospace Certification Package
- Optional Chipset and Reference Design