IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AXI IP > AMBA AXI3 Assertion IP

AMBA AXI3 Assertion IP

Overview

AMBA AXI3 Assertion IP provides an smart way to verify the ARM AMBA AXI3 component of a SOC or a ASIC. The SmartDV's AMBA AXI3 Assertion IP is fully compliant with standard AMBA AXI3 Specification and provides the following features.

AMBA AXI3 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA AXI3 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant with the latest ARM AMBA AXI3 Protocol Specification.
    • Supports all AXI3 data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    • Separate address, data and response phases. Separate read and write channels.
    • Support for burst-based transactions with only start address issued.
    • Write strobe support to enable sparse data transfer on the write data bus.
    • Narrow transfer support.
    • Unaligned address access support.
    • Ability to issue multiple outstanding transactions.
    • Out of order transaction completion support.
    • Protected accesses with normal/privileged, secure/non-secure and data/instruction.
    • Support for Write data phase before Write address phase.
    • Ability to configure the width of all signals.
    • Support for bus inactivity detection and timeout (configuration parameter and dynamic change of inactivity timer).
    • Write data and read data interleaving support.
    • Configurable write and read interleave depth.
    • Programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
    • Atomic access support with normal access, exclusive access and locked access
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV AXI3 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure AXI3 Assertion IP functionality.

    Benefits

    • Runs in every major formal and simulation environment.

    Block Diagram

    AMBA AXI3 Assertion IP Block Diagram

    Deliverables

    • Detailed documentation of Assertion IP usage.
    • Documentation also contains User's Guide and Release notes.

    Technical Specifications

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