AMBA ACE4 Synthesizable Transactor provides a smart way to verify the ARM AMBA ACE4 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA ACE4 Synthesizable Transactor is fully compliant with standard AMBA ACE4 Specification and provides the following features
AMBA ACE4 Synthesizable Transactor
Overview
Key Features
- Compliant with the latest ARM AMBA ACE4 Protocol Specification.
- Supports ACE4 Master and Slave.
- Supports all ACE4 data and address widths.
- Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
- Supports constrained randomization of protocol attributes.
- Separate address, data and response phases. Separate read, write and snoop channels.
- Support for burst-based transactions with only start address issued.
- Slave and Master support fine grain control of response per address or per transaction.
- Programmable wait states or delay insertion on different channels.
- Ability to inject errors during data transfer.
- Write strobe support to enable sparse data transfer on the write data bus.
- Narrow transfer support.
- Unaligned address access support.
- Ability to issue multiple outstanding transactions.
- Out of order transaction completion support.
- Protected accesses with normal/privileged, secure/non-secure and data/instruction
- Ability to configure the width of all signals.
- Support for bus inactivity detection and timeout(configuration parameter and dynamic change of inactivity timer).
- Configurable WID signal enable support.
- Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
- Atomic access support with normal access and exclusive access
- Longer bursts up to 256 beats.
- Quality of Service signaling.
- Multiple region interfaces.
- User signaling support.
- Ability to break longer bursts into multiple shorter bursts
- Supports unmapped region address accesses
- AWCACHE and ARCACHE Attributes.
- Low-power Interface support
- ACE4 specific features
- Supports functionality to verify ACE4 and Cache Coherent Interconnect functionality for cache.
- Supports all ACE4 transaction types including Snoop, Evict, WriteEvict, Barrier and Distributed virtual memory (DVM) transactions.
- Support for multiple outstanding ACE4 transactions.
- Supports all write/read responses and snoop responses.
- Support for cache model and snoop filtering
- Fine grain control of Initiating Master transaction including main memory access.
- Fine grain control of Interconnect generated snoop transaction to snooped Masters.
- Fine grain control of Interconnect generated main memory access transactions.
- Fine grain control of Snooped Master response to a snoop transaction.
- Programmable Timeout insertion.
- Rich set of configuration parameters to control ACE4 functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Callbacks in Master and Slave for various events.
- Status counters for various events on bus.
Benefits
- Compatible with testbench writing using SmartDV VIP's
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the AMBA ACE4 Synthesizable testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all class, task and functions used in verification env
- Documentation contains User's Guide and Release notes