IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AXI IP > AHB/AXI4-Lite to AXI4-Stream Bridge

AHB/AXI4-Lite to AXI4-Stream Bridge

Overview

The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus.

Designed for ease of integration, it optionally implements clean clock-domain crossing (CDC) boundaries, allowing the peripheral and host system to operate in different clock domains.

The MM2ST core is rigorously verified, LINT-clean, and scan-ready. It is available in synthesizable Verilog and FPGA netlist forms and ships with everything required for successful implementation, including a testbench, simulation, and synthesis scripts, and comprehensive user documentation.

Key Features

  • Memory-Mapped to Stream Bridge
    • Bridges AXI4-Stream and APB register interfaces of a peripheral to a 32-bit or 64-bit AHB or AXI-Lite subordinate port
    • Optionally implements clean CDC boundaries between the pe-ripheral and the host bus clocks
    • Performs data-width conversion from/to the peripheral’s buses data widths to/from the width of the memory mapped bus
  • Interfaces
    • Host Interface:
      • 32-bit or 64-bit AHB or AXI4-Lite Subordinate
      • Interrupt with maskable sources
    • Peripheral Interface
      • A configurable-width (up to 512 bits) AXI4-stream per direction
      • 32-bit APB interface for CSR access
      • Configurable number of GPIOs
    • Handshaking signals for external DMA controller
  • Synthesis-Time Configuration Options
    • Data width for the AXI-Stream interfaces
    • Data width of the memory-mapped interface (32 or 64 bits)
    • Number of general-purpose in-put and output pins
    • AHB address width
    • Instantiation of the APB manager port
    • APB address offset and width
    • Instantiation of CDC logic
    • FIFO sizes
  • Deliverables
    • Synthesizable RTL or FPGA netlist
    • Verilog testbench & sample test cases
    • Simulation & synthesis scripts
    • Documentation

Block Diagram

AHB/AXI4-Lite to AXI4-Stream Bridge Block Diagram

Technical Specifications

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