The AES engine IP is a high-performance cryptographic engine operates in AES NIST Federal information processing standard FIPS-197. It supports AES-ECB AES-XTS mode and 128/256 key-length both encryption/decryption. The core engine supports 128/256/512 data width operation. The encryption and decryption engines are-full duplex to provide high performance and support on-the-fly key update. YEESTOR's AES engine IP is delivered with complete development package for the ease of use in both FPGA and SoC design.
AES Engine IP
Overview
Key Features
- Comply to NIST FIPS PUB 197
- Support ECB (Electronic Codebook) implementation per NIST SP800-38A
- Support AES-XTS implementation per NIST SP800-38E
- Drop-in module for ASIC & FPGA
- Signal Clock Domain
- Support Data Length 128/256/512-bits
- Support Key Length 128/256-bits (※192 bits option)
- Support automatic roundkey generation inside the core.
- Support on-the-fly key update while data processing
- Mode Support: ECB (Electronic Code Book), XTS (Tweakable Codebook mode)
Benefits
- Time-to-Market
- Comply to NIST FIPS PUB 197
- Silicon Proven
Block Diagram
Applications
- PCIe-NVMe Client/Enterprise SSD controller
Deliverables
- RTL code
- Verilog direct test verification environment
- Synthesis script and constraint for ASIC and FPGA
- Documentations
- Datasheet
- Integration guide
- Programming guide
- Register specification
- Training Course
Technical Specifications
Maturity
In production (silicon proven)
Availability
available
Related IPs
- AES Multi-purpose crypto engine
- AES Encryption & Decryption IP Core − Single Configurable Block Cipher Mode
- AES Encryption & Decryption IP Core − Programmable Block Cipher Modes
- Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode
- AES-GCM Authenticated Encrypt/Decrypt Engine
- AES-GCM Ultra-low latency crypto engine