AES

Overview

The AES core is a drop-in module that includes
the following functions:
• 128/192/256-bits key size
• Automatic Roundkey calculation
• Encryption or decryption functions are implemented in the core

Key Features

Implements AES (Rijndael) to latest NIST FIPS PUB 197
Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
Single clock
Supports 128/192/256-bits key size
Same core can be used for encryption and decryption
Automatic Roundkey generation inside the core
Update Key is allowed if an encryption or decryption process is running
ECB (Electronic Code Book) and CBC (Cipher Block Chaining) are supported
> 200Mbps @ 125MHz (AES-128)800
> 170Mbps @ 125MHz (AES-192)
> 150Mbps @ 125MHz (AES-256)
Full synthesizable RTL VHDL design (not delivered) for easy customization

Block Diagram

Applications

AES-128 core may be used in applications related to MPEG-TS stream encryption, or any other encryption applications.

Deliverables

Datasheet
Netlist for core generation
VHDL top file
VHDL source code: can be delivered as an option under NDA and other specific clauses

Technical Specifications

Availability

Available

Request Info

AES