8-bit, 1MSPS low-noise high accuracy analog-to-digital converter

Overview

The 8-bit, 1Msps ADC is a single-ended cyclic ADC based on 1.5-bit/conversion architecture with error correction. It consists of single to differential amplifier and fully differential cyclic ADC. Reference voltages are internally derived from externally supplied 1.45V voltage reference and 15uA current reference. Non-overlapping and sampling clocks are derived from a 10MHz external clock. ADC is implemented in 40nm CMOS from Global Foundries with 6L1x_1T6x_1T18x_LB process options.

Key Features

  • Single to differential ADC driver amplifier
  • Fully differential Cyclic ADC with bit controllable unsigned or signed output
  • 1.5 bit MDAC/ADC architecture with error correction
  • Internal reference buffers and generator from single 1.45V voltage reference
  • 1MSPS guaranteed sampling rate
  • 7.7 bit ENOB typical
  • Linearity
    • DNL = ±0.11 LSB typical
    • INL = -0.3/+0.2 LSB typical
  • 48.8 dB SNR / 48.0 dB SNDR / 60.7 dB SFDR typical with 50.7kHz input (1.45 Vpp input, 1MSPS)
  • Output clock available
  • 50MHz clock input or 10MHz clock input select
  • Active chip area 0.044mm2
  • 1.9 mW typical normal power consumption / 34 uW typical in power down
  • -40°C to +125°C operational temperature range

Block Diagram

8-bit, 1MSPS low-noise high accuracy analog-to-digital converter Block Diagram

Technical Specifications

TSMC
Pre-Silicon: 28nm
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Semiconductor IP