This macro-cell is a low-power, precision, general purpose 3.3V 6MHz ±1% PVT internal oscillator core aimed for clock generation. A 7 bit digital bus allows frequency adjustment against process variations.
It features a self-biased, built-in references.
The core can be easily retargeted to any other frequencies between 1MHz and 30MHz and other CMOS technology that includes poly resistors.
6MHz ±1% PVT 3.3V Low Power Oscillator in Silterra 0.18um
Overview
Key Features
- 6MHz +/- 1% PVT after trimming
- Supply 3.3V +/- 10%
- Low power (20uA)
- Low TC (>115ppm/oC)
- 7-bit trimming
- Self-biased, built-in references
- Indicative area: 0.015mm2
- Load capacitance: <100fF
Technical Specifications
Foundry, Node
Silterra 0.18 um
Maturity
GDS Available
Silterra
Pre-Silicon:
180nm
Related IPs
- 6MHz ±1% PVT 1.8V Low Power Oscillator in Silterra 0.18um
- I2C Controller IP – Slave, SCL Clock only, principally for configuring registers in mixed-signal ICs with low noise or low power requirements
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- Low power 32-bit processor supporting single precision floating point in hardware
- HHGrace 0.18um 3.3V RC Oscillator
- HHGrace 0.18um 3.3V RC Oscillator