The ATO00064X8NX150FPS3NA is organized as a 64x8 one-time programmable (OTP). This is a type of non-volatile memory fabricated in Nexchip 0.15um 3.3V logic process. The OTP can be widely used in chip ID, security key, memory redundancy, parameter trimming, configuration setting, feature selection, and PROM, etc.
64x8 Bits OTP (One-Time Programmable) IP, Nexchip 0.15um 3.3V Logic Processes
Overview
Key Features
- Fully compatible with Nexchip 0. 15um 3.3V logic processes
- Wide operating voltage range:
- – Read voltage: 1.62–3.63 V VDD and VDDP
- – Program Voltage: 3.45 V ± 5% VDDP and 1.62–3.63 V VDD
- Programming time: 10-µs program time per bit
- Access time: 200-ns read cycle time (Tcd max. 100 ns)
- Wide temperature range: -40 °C to 125 °C for read and 10 °C to 40 °C for program
Benefits
- High yield performance
- Small IP size
- Good retention reliability
- Customization upon request
- No charge pump is required for programming
- Programming with true "electro-migration" and without any device damage
- Wide operating temperature range
- Silicon characterized
Deliverables
- Datasheet
- Verilog behavior model and test bench
- Timing library
- LEF File
- Phantom GDSII database
Technical Specifications
Foundry, Node
Nexchip 0.15um 3.3V Logic Processes
Maturity
Silicon Proven & Ready for Production
Related IPs
- Embedded OTP (One-Time Programmable) IP, 64x8 bits for 3.3V Logic
- Embedded OTP (One-Time Programmable) IP, 64x8 bits for 3.3V Logic
- Embedded OTP (One-Time Programmable) IP, 64x8 bits for 1.8V/3.3V Logic
- Embedded OTP (One-Time Programmable) IP, 64x8 bits for 3.3V Logic_MR
- Embedded OTP (One-Time Programmable) IP, 512x8 bits for 3.3V Logic
- 64x8 Bits OTP (One-Time Programmable) IP, UMC 55nm ULP standard CMOS core logic Process