64-bit Multiprocessor with Level-2 Cache-Coherence

Overview

AndesCore™ AX45MP 64-bit multicore CPU IP is an 8-stage superscalar processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMAC-FD)” extensions, “C” 16-bit compression instructions, DSP/SIMD ‘P’ extension (draft), user-level interrupt ‘N’ extension, and Andes performance/ functionality enhancements for faster memory accesses and branch handling, plus Andes Custom Extension™ (ACE) to add user-defined instructions. It features MMU for Linux based applications, branch prediction for efficient branch execution, level-1 instruction/data caches and local memories for low-latency accesses.

The AX45MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. Coherence manger implements MESI protocol to manage level-1 cache coherence, including I/O coherence for cacheless bus masters. Other AX45MP features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, and QuickNap™, PowerBrake, and WFI for power management.

Key Features

64-bit in-order dual-issue 8-stage pipeline CPU architecture
Symmetric multiprocessing up to 4 cores
Level-2 cache and cache coherence support
AndeStar™ V5 Instruction Set Architecture (ISA). Compliant to RISC-V ISA IMACFDN, with Andes performance/functionality extensions
Floating point extension DSP/SIMD ISA
Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
64-bit architecture for memory space over 4GB
16/32-bit mixable instruction format for compacting code density
Branch predication to speed up control code
Return Address Stack (RAS) to speed up procedure returns
Memory Management Unit (MMU), Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PMA)
Level-1 and level-2 cache controllers with 64-byte cache line size
Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
Enhancement of vectored interrupt handling for real-time performance
Advanced CoDense™ technology to reduce program code size

Block Diagram

Applications

High performance application processor
Machine/Deep learning acceleration
Video and image processing
Large-scale network controllers
ADAS/V2X/IVI

Technical Specifications

Availability

Now

Request Info