600Mbps Low Power D2D Interface in 16nm
Overview
Custom die-to-die interface in 16nm process technology. The I/O cell is bi-directional and has two modes of operation: standard rail-to-rail swing or a custom low-noise pseudo-differential interface. Rx cells have a weak pull-down feature.
Key Features
- Core Device: 0.8V
- I/O Device: 1.8V Standard
- Core: Uses SVT only
- PAD: Flip-chip/D2D packaging, no wire-bond option
- Cell: 50um x 5um
- VDD Core: 0.8V±10%, 0.7V/0.65V
- Temperature: -40C to 125C
- ESD: Target 500-1kV HBM for robust MCM assembly, 500V CDM
Deliverables
- Verilog Models for all I/O, behavioral, and stubs.
- LEF's
- CDL netlists for DRC and LVS
- GDS
- IBIS
- Liberty TIming Models
- User Guide and Documentation
Technical Specifications
Foundry, Node
16nm
Maturity
Pending Silicon Validation
Availability
Immediate
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