6.5V ESD Clamp in 180nm Technology
Overview
Standalone 6.5V ESD Power Clamp in 180nm technology for use in wirebond or flipchip.
Key Features
- 1.8V/5V FETs
- 1P6M with 2fF MiMs
- Temperature: -40C to 125C
- Metallization for cell is M1-M5
- ESD targets of >2kV HBM JEDEC, 500V CDM
- Lath-up Immunity
- Cell Size: 60um x 80um (no fixed orientation)
Deliverables
- Verilog Models for ESD
- LEFs
- CDL netlists for DRC and LVS
- GDS Layouts
- Spectre scs models for simulation
Technical Specifications
Foundry, Node
180nm
Maturity
Silicon-Proven
Availability
Immediate
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