5G-NR LDPC Encoder
Overview
The Creonic 5G LDPC Encoder IP Core provides a perfect solution for this new LDPC structure with a high level of flexibility while maintaining high throughput and low latency as required by the standard
Key Features
- Support for 3GPP Release 15 5G LDPC decoding
- Support for base code rates from 22/68 to 22/26 for basegraph 1
- Support for base code rates from10/52 to 10/14 for basegraph 2
- Puncturing is included in the cores
Benefits
- High-throughput design.
- Low-power and low-complexity design.
- Block-to-block on-the-fly configuration.
- AXI4-Stream handshaking interfaces for seamless integration.
- •Available for ASIC and FPGAs (AMD Xilinx, Intel)
Applications
- 5G modem chipset for base station (BS) or user equipment (UE)
- Applications with the highest demands on forward error correction
- Applications with the need for a wide range of code rates and block length
Deliverables
- VHDL source code or netlist
- HDL simulation models
- VHDL testbench
- Bit-accurate Matlab, C or C++ simulation model
- Comprehensive documentation