IFA consists of 3-stages amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digital converter for 2-bits digital output.Each stage of the amplifier has differential input and output. Gain is sequentially reduced from the last stage to the first stage. Also gain can be fixed by the digital code DAC<9:0>. Output voltage supported by AGC system on differential load at 500 Ohm or 1000 Ohm compounds:
- for sine waveform 200 mV (peak-to-peak);
- for noise signal 480 mV (peak-to-peak).
The block is fabricated on SMIC CMOS 018 um technology.
5 to 20 MHz Intermediate-frequency amplifier
Overview
Key Features
- SMIC CMOS 0.18 um
- Wide gain range (0…62 dB)
- Low group delay time ripple vs. frequency and gain
- Analog and digital output modes
- Built-in AGC detector with external capacitor
- On-board bias compensation on dc voltage in each amplifier stage and output buffer
- Usage of ADC for the purpose of receipt of digital output signal
- Portable to other technologies (upon request)
Applications
- Receivers
- Transceivers
- Navigation systems
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
SMIC CMOS 018 um
Maturity
silicon proven
Availability
Now
SMIC
Silicon Proven:
180nm
G