4Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40nm ULP 1.1V/2.5V Process

Overview

The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSMC 40nm ULP standard CMOS core logic process. The OTP can be widely used in chip ID, security key, memory redundancy, parameter trimming, configuration setting, feature selection, and PROM, etc.

Key Features

Fully compatible with standard TSMC 40nm ULP 1.1V/2.5V CMOS logic process
Low voltage: 1.1V+/-10% read and 2.65V+/-5% program
High-speed program: 10us single-bit programming and up to 4-bit programming
High-speed read: 25Mhz read clock (40ns cycle time) per 32-bit word
Additional rows to store any information
Built-in fuse protection circuits
Deep sleep by cutting down VDD for SoC power saving

Benefits

Small IP size
Low program voltage/current
Low read voltage/current
High reliability
Silicon characterized and qualified

Deliverables

Datasheet
Verilog behavior model and test bench
Timing library
LEF File
Phantom GDSII database

Technical Specifications

Foundry, Node

TSMC 40nm ULP 1.1V/2.5V

Maturity

Silicon Proven & Ready for Production

Availability

Now

TSMC

Silicon Proven: 40nm LP

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