<4Gbps Low Power D2D Interface in TSMC 16nm & 28nm

Overview

A <4Gbps, Wide I/O Compatible, Die to Die Interface in TSMC 16nm and 28nm.

This silicon proven die to die interface includes IP in both TSMC 16nm FFC/FFC+ and 28nm HPM/HPC/HPC+. The I/O cells for both versions of the library are defined as TX only and RX only. The cells have two modes of operation: standard full rail to rail swing or a custom low noise psuedo-differential interface. The RX cells have a weak pull-down feature. The library is designed for Flip-chip/Die to Die packaging only, with no Wirebond option. Both library options have a common power bus architecture that when the cells are abutted, will feed through. There are no Power or Ground Pad/Cells, however all VDD and VSS connections will be made to the Core domain in upper metals. Both library options are ultra-low power, have a small footprint, MCM compliant, and have HBM & CDM robustness.

Operating Conditions for 16nm

Parameter Value
VDDIO 0.8V
I/O Device 1.8V
Core Use SVT Only
Cell Size 50x28.06um
BEOL M8 & below
VDD Core 0.8V +/- 10%
Temperature -40C to 125C
Operational Bit Rate 2Gbps1

Operating Conditions for 28nm

Parameter Value
VDDIO 0.9V
I/O Device 1.8V
Core Use SVT Only
Cell Size 50x25um
BEOL M8 & below
VDD Core 0.9V +/- 10%
Temperature -40C to 125C
Operational Bit Rate 2Gbps1

 Cells for 16nm D2D

Cell Name Width Description
UF_TX 50x25um TX Cell
UF_RX 50x25um RX Cell

Cells for 28nm D2D

Cell Name Width Description
UD_TX 50x30.5um TX Cell
UD_RX 50x30.5um RX Cell

Block Diagram

<4Gbps Low Power D2D Interface in TSMC 16nm & 28nm Block Diagram

Technical Specifications

TSMC
Pre-Silicon: 16nm , 28nm
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Semiconductor IP