40G I.3 BCH Encoder/Decoder for ITU G.975.1

Overview

The IPrium-40G-I.3-BCH-Codec IP core implements "Concatenated BCH super FEC" with BCH(3860, 3824) and BCH(2040, 1930) forward error correction algorithms for optical lines and is fully compatible with ITU-T G.975.1 (super-FEC for 2.5G, 10G and 40G optical networks).

Key Features

  • Fully synchronous design, using single clock
  • Fully synthesizable drop-in module for FPGAs
  • Optimized for high performance and low resources
  • Low implementation loss
  • Fully verified and real-time tested on a FPGA based development platform
  • Considerations for easy ASIC integration
  • Validated on IPrium Evaluation Boards

Deliverables

  • VQM/NGC/EDIF netlists for Intel (Altera) Quartus Prime, Xilinx Vivado/ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
  • IP Core testbench scripts
  • Design examples for Intel (Altera), Xilinx, Lattice, and Microsemi (Actel) evaluation boards
  • Free 1 year warranty and support period

Technical Specifications

Maturity
Silicon proven
Availability
Now
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Semiconductor IP