3D OpenGL ES 1.1 GPU (Graphics Processing Unit)

Overview

D/AVE 3D is cost-efficient IP core for 3D graphics applications. This core is available for FPGAs, ASICs and SOCs, specifically designed for the embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software.

Key Features

  • Low resource usage
    • Low gate count ( ~1Mio. Gates for ASIC)
    • Low internal memory requirements ( ~125 K Memory Bits)
    • ~70K Logic elements for FPGAs
  • Offers a wide range of graphical primitives
    • Lines, Triangles, Quadrangles
  • Prepared for easy SoC integration
    • ALTERA AVALON support
    • ARM AMBA-AHP, ARM AMBA-APB Bus support
    • Performance robust to high memory latency
    • Single clock domain architecture
  • High Performance
    • 100 Mio. Pixels/Second fill rate (100 MHz).
    • 6,6 Mio. triangles throughput (100 MHz.)
    • Early-Z-Test
  • High Quality Rendering
    • Anti-Aliasing and Sub-Pixel accurate rendering
    • Edge-Based-Filtering for image scaling
    • Per-Primitive-Anti-Aliasing (settable per edge)
    • Static dithering at Framebuffer write back to enhance RGB565 output
  • Fully programmable Transform and Lighting Engine
  • Textures
    • 2048 x 2048 Texture size
    • Flexible texture color format handling
    • Texture compression
    • Texture offset swizzeling
  • Framebuffer
    • 2048 x 2048 supported
    • ARGB8888, ARGB4444, ARGB1555, RGBA5551, RGB565, AL88, AL44, A8
    • Blend Modes - Blend, Multiply, Darken, Lighten

Benefits

  • 100% cache hit rates
  • No latency from external data
  • Internal pipeline latency ignored
  • 100 MHz.

Deliverables

  • Documentation (HTML)
  • VHDL
  • Driver
  • Ready to use NIOS project, based on Altera Evaluation Kit & Tools
  • PC based emulation set-up
  • Ready to use demo
  • Application SW templates

Technical Specifications

Maturity
silicon proven
Availability
Now
TSMC
Pre-Silicon: 40nm LP
×
Semiconductor IP