2D/3D Vector Graphics Accelerator / GPU (Graphics Processing Unit)

Overview

D/AVE HD is a cost-efficient, highly configurable IP core for 2D and 3D graphics applications. The variants of the core are available for FPGAs, ASICs and SOCs. The high customizability allows footprint and power optimized variants, e.g. for wearable applications or high-volume MCUs, up to feature-rich and powerful variants for automotive infotainment and professional solutions.

Key Features

  • D/AVE HD is an evolution in the D/AVE family supporting high quality 2D rendering and basic 3D rendering for displays up to 4K x 4K. With its high customizability D/AVE HD targets modern graphics applications in the Industrial, Medical, Military, Avionics, Automotive and Consumer markets. D/AVE HD is designed to be fast with powerful functionality and at the same time optimized regarding size and footprint. Its footprint optimized variants are especially suitable for low-power wearable products.
    • Full Khronos compliant OpenVG 1.1 API (optional)
    • High-performance pixel pipeline (producing max 1 pixel/cycle)
    • Advanced Graphics Features:
    • Basic 3D graphics operations
    • Rotation Engine
    • Composition Engine
    • Framebuffer- and Texture-compression
    • Transformation & Warping Support
    • Optimized Power Management Support
    • Hardware multi-threading support
    • Hardware system security support

Benefits

  • Highly modular design allowing customizability at synthesis time.
  • OpenVG support (optional)
  • Designed for high perormance: 100% cache hit rates, no latency from external data,
  • Internal pipeline latency ignored.
  • Support up to 4kx4k reslotions.

Applications

  • Wearables
  • Smart Watches
  • GUIs
  • Whitegoods
  • Entertainment devices
  • Consumer devices
  • Dashboards
  • Flight Displays
  • Video Systems
  • Test&Measurement
  • Industrial Control

Deliverables

  • Documentation (HTML)
  • VHDL (IP Core) including test bench
  • ANSI-C Driver for bare metal
  • OpenVG driver (option)
  • Ready to use NIOS project, based on Altera Evaluation Kit & Tools
  • PC based pixel exact emulatior
  • Ready to use demos (as C source code)
  • Application SW templates

Technical Specifications

Maturity
silicon proven
Availability
Now
TSMC
Pre-Silicon: 40nm LP
×
Semiconductor IP