32G Multi Rate SerDes PHY - GlobalFoundries 22FDX

Overview

Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are employed to achieve robust performance across process and operating conditions. This allows a maximum of flexibility and reduces the effort for migration to alternate target technologies. The design itself is complemented by the comprehensive advanced verification and modeling methodology employed by Extoll.
A single SerDes PHY block can consist of up to 4 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 1.25 to 32Gbps. Multiple PHY blocks can be combined to construct wider links.Moreover, the PHY IP can be adapted to custom requirements easily.
The IP enables the smallest footprint of a multi rate multi protocol and long reach SerDes Interface in the industry with lowest power consumption and channel support of up to 30 dB insertion loss.
Extoll´s SerDes is best suited to support high-speed data applications in Industrial, Aerospace, Automotive, HPC and QC segments.

Key Features

  • Line rates from 1.25 up to 32Gbps
  • PCIe up to Gen4.0
  • PIPE interface
  • Ethernet 10G, 25G, 50G, 100G
  • JESD204B/C
  • SATA up to rev 3.0
  • RapidIO up to rev 4.0
  • Infiniband up to FDR
  • Programmable transmitter with equalizer
  • Programmable RX linear equalizer
  • Programmable RX DFE
  • Digital high speed PLL
  • Pattern Generator for diagnostics
  • Concurrent Eye Monitor for equalization and channel analysis
  • Far End and Near End Loopbacks
  • Analog testbus

Applications

  • High-Speed I/O Interfaces: PCIe, RapidIO, SATA, others
  • Networking equipment and interfaces: for Ethernet standards, Infiniband, others
  • High-speed data-converters: DAC, ADC, etc.
  • Interfacing electronic equipment using high-speed optical interfaces
  • Serializer based proprietary protocols on board or back-plane level and with cabled connections
  • Low-latency Die-to-Die interconnects based on lean and cache-coherent protocols: CHI, AXI, AXI-lite, etc.

Deliverables

  • Front- and backend integration views
  • LIB, LEF, CDL netlist, GDSII layout
  • Fast Verilog simulation models
    • Functional abstract, functional
    • RNM (real number model) (optional)
  • IBIS/AMI models
  • Sample testbench
  • PIPE RTL (optional)
  • Die-to-Die/CHI Controller RTL (optional)
  • Documentation
    • User Manual, Integration & DfT Guide
    • Control and Status Registers Manual
    • IPXACT memory map
    • Electrical characteristics, Silicon Report

Technical Specifications

Foundry, Node
GlobalFoundries 22FDX
Availability
28G available, 32G planned; MRAM support for automotive: planned 2H/2023; SR (die-to-die): planned 1H/2023 with < 4mW/Gbps - optional with low-latency controller for CXI and AXI
GLOBALFOUNDRIES
Silicon Proven: 22nm FDX
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Semiconductor IP